One major challenge for wireless receivers to maintain information fidelity involves the demodulation of faded signals in noisy environments. Typical demodulation techniques for M-ary quadrature amplitude modulated (M-QAM) signal utilize variants of coherent demodulation. This paper explores deep learning (DL), specifically by using a proposed architecture recurrent-attention networks to compliment, or even overcome the limitations of demodulating M-QAM symbols. The proposed model is shown to outperform the benchmark coherent demodulator and other DL-based demodulators such as convolutional neural network (CNN), recurrent neural network (RNN) and the hybrid of both up to 5 dB learning gain at a lower model complexity and requires less memory usage.

This paper presents a data-driven unsupervised Deep Learning-based joint channel estimation and signal detection method for a narrowband wireless communication system. Our proposed Deep Learning-based architecture uses a Variational Autoencoder (VAE) that can combat the effects of additive white Gaussian noise and Rayleigh fading by encoding the input into a lower dimensional representation as the latent space outputs. The lower dimensional representation is used to extract the symbol information and is classified to the corresponding symbols of the transmitted signal using a classifier. We propose two approaches for the VAE-based architecture by using a parallel 1-D VAE and a joint 2-D VAE that takes different signal representations. From our simulation results, the proposed VAE-based architectures can achieve BER performance improvements over a deep Convolutional Neural Network approach and corre-lator detector.

M-ary quadrature amplitude modulation (M-QAM) modulated signal is commonly used in digital telecommunication systems for its arbitrarily high spectral efficiencies limited only by the noise level and linearity of the communications channel. Typical demodulation techniques for M-QAM signal utilize variants of coherent demodulation. This paper aims to exploit the robustness of deep learning, specifically by using neural networks to demodulate M-QAM symbols. This is achieved with simulated time-domain baseband M-QAM signals across a range of channel impairments namely additive white Gaussian noise, DC offset and I/Q imbalance. The presented results show an improvement when utilizing deep learning over optimal receiver.

In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source (

This paper introduces a design methodology that reduces the fundamental trade-off between linearity and power added efficiency (PAE) in CMOS power amplifier (PA). In our work, a stacked power block (SPB) has been proposed to mitigate the effect of gate–source capacitance (Cgs), thus linearizing the PA. Each stage is biased independently to shape the gain profile, either to be in the expanded mode or in the compressed mode, in which once combined it delivers a flat gain response and confirming the linearity performance. Efficient PI input and output matching networks are proposed to ensure no further distortion, once connected to the 50 Ω source and load. The PA achieves input and output return losses of less than −10 dB from 2.40 to 2.50 GHz. At the center frequency of 2.45 GHz, the SPB-PA achieves a gain of 10 dB and it is unconditionally stable. The proposed gain shaping linearization technique delivers a maximum linear output power (Poutlinmax) of 19.8 dBm with only 3.3 dB back-off from maximum output power (Poutmax) of 23.1 dBm. The SPB-PA meets the WLAN specification with linear PAE of 30% and peak PAE of 36.1%. The proposed SPB-PA reduces the fundamental trade-off between linearity and efficiency. Integration of this PA in wireless SoC shall reduce the chip’s overall power consumption.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures.

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load. We also utilize the DAAPD to optimize the PA when subjected to process-voltage-temperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPD-PA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.