In this study, a six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi-finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place-and-route (P&R). The proposed library was analysed and compared with two eight-track multiplier layout libraries in the cell and block design level. Based on the place-and-route results of ISCAS'85 benchmark circuits, the proposed six-track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.

Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%~5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design.

In VLSI semi-custom design approach, power-optimal standard cell library selection for a given block design requires time-consuming iterative processes. This paper presents a framework to select a standard cell library that can result in near-optimal power while satisfying targeted frequency. The framework relies on neural network model to quickly predict the total power of a block design associated with a given standard cell library in order to speed up the synthesis process. The experimental result based on various synthesized benchmark circuits demonstrated the effectiveness of proposed framework for near-optimal standard cell library specification.

Development of renewable power generation systems (RPGSs) is continually increasing worldwide with Germany, China, Japan, Italy and the USA are the leaders contributing to the largest development in each region. Due to the increasing number of RPGSs connected to the utility grid, power quality, safe operation, and islanding protection of RPGSs are becoming important issues, among others. One of the most important elements is the current control technique that must meet the requirements for grid interconnection according to international standards and practices. The RPGS itself must be safe and highly efficient for reliable and secure grid interconnection operations. This paper presents a review of the state-of-the-art of the current control techniques for three-phase grid-interconnection of RPGSs. Several current control architectures, their operations including advantages and disadvantages were discussed. Performance comparison and evaluation of several controllers were also reviewed.

A comparative review between different algorithms for maximum power point (MPP) tracking is presented, particularly focusing Numerical Method (NM) techniques. This paper presents a wide range of efficient NM schemes which have been neglected by most of the MPPT review papers. As, NM techniques are one of the simplest and fastest tracking algorithms. These techniques offer advantages of exact MPP tracking, standalone applications, flexible searching step sizes and no steady state oscillations. In addition, many different MPPT schemes are discussed and compared with the NM techniques. There are many ways of grouping and categorizing the MPPT algorithms for the Photovoltaic (PV) Array. However, evaluation of the NM schemes in comparison with other techniques is provided effectively through analog and digital classification, in terms of implementation and circuitry involved. Therefore, a comparative review majorly focusing on the importance of NM schemes to track the MPP is presented in comparison with other techniques, through analog and digital classification.

This paper presents a three-level hybrid boost converter based on T-type neutral point clamped inverter. The main advantage of the proposed converter is the capability of high voltage conversion ratio without using extreme duty cycle, high-frequency transformer, and coupled inductor. The performance of the proposed three-level hybrid boost converter has been simulated using PLECS software.

Multiplications are often involved in Digital Signal Processing such as for digital filters and FFT (Fast Fourier Transform). It requires high speed multipliers and logic components (such as adders, subtractors, and shifters). Processing speed is always critical for Digital Signal Processing, and there are many attempts to reduce the processing latency that may cause performance issues on the end product. There has been a number of parallel multiplication approaches proposed to speed up computation. This paper aims to design and implement several parallel multiplication approaches using Field Programmable Gate Array (FPGA). These approaches make use of the resources in FPGA to achieve fast multiplication. The parallel methods implemented and compared in this paper include partitioning of multiplicands for parallel multiplication, hybrid Look-up tables (LUT) parallel multiplication, and Wallace Tree Multiplication algorithm. Comparison is made based on the number of processing cycles and also the amount of resources used in the FPGA through simulation. The proposed designs utilized lesser processing cycles (5 cycles) for a single process by using the FPGA resources effectively.

We develop a model for OFDM based VLC systems capable of predicting the SNR at the receiver. The proposed models are more feasible for practical application. They are experimentally evaluated and the limitations presented.