This paper presents a compact circularly polarized (CP) antenna with an integrated higher order harmonic rejection filter. The proposed design operates within the ISM band of 2.32 GHz– 2.63 GHz and is suitable for example for wireless power transfer applications. Asymmetrical truncated edges on a square ring create a defected ground structure to excite the CP property, simultaneously realizing compactness. It offers a 50.5% reduced patch area compared to a conventional design. Novel stubs and slot shapes are integrated in the transmission line to reduce higher (up to the third) order harmonics. The proposed prototype yields a -10 dB reflection coefficient (S11) impedance bandwidth of 12.53%, a 3 dB axial ratio bandwidth of 3.27%, and a gain of 5.64 dBi. Measurements also show good agreement with simulations.

This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple and fast enough to collect the assertion results from assertion checker. In our work, collection module is implemented as arbiter and memory blocks. Case studies have been conducted on 8-bit counter and 8-bit FIFO with 10 assertions and 8 design bugs. Comparison has been done with assertion checker derived from MBAC approach in terms of checker's size. The comparison has showed that the checker size can be reduced further for 17.39%.

This paper focuses on the development of non-contact heart rate measurement based on video analysis. This project implements an RGB camera (OV2640 with ESP32 Cam) and an FTDI Programmer which enables the sensor to record videos from a subject at a distance of 20 cm. The Region of Interest (ROI) of the facial skin tissue was detected by using Cascade Object Detector (COD) which can detect object categories whose aspect ratio does not vary significantly. Then, the Independent Component Analysis (ICA) was applied by extracting distinct source signals (red, blue and green channels) from the observed mixed colour signals. Next, the average pixel of ROI was calculated based on red, green and blue facial pixel at given time. Finally, the heart rate was extracted from the frequency spectrum of the average pixel. The performance of the developed contactless system was compared with the fingertip pulse oximeter (Oxitech) by means of percentage of error (PE). The lowest range of PE is between 0 to 5.62 % whereas the highest PE is 22.54 %. The highest error was due to incorrectly captured ROI of facial skin area as well as due to the movement made during the recording session. Meanwhile, the average time for the developed system to process the heart rate of the subject is 4.51 minutes. In future, a robust ROI algorithm can be adopted to reduce error contributed by incorrectly ROI selection. Other than that, this project has a potential to contribute to the area of contactless measurement of oxygen saturation.

Analytical surveillance can perform the surveillance tasks much more efficient comparing to operator manual monitoring. This had made it getting increased market's interest in recent years. Commonly, closed circuit television (CCTV) is used for security surveillance. However, CCTVs are purely vision output. These silent videos may not provide complete picture of the happening. Sound detection is incorporate into vision surveillance for enhancement. Sound detection is able to detect abnormal sound although happen at camera blind spots or due to intentional blocking. In this paper, we propose to use microcontroller embedded system to enhance current CCTV system. Proposed abnormal sound embedded system is to carry out the sound detection, audio processing and analysis. This study is using only single microphone for sound detection. Audio amplitude and frequency range are targeted feature extracted from Fast Fourier Transform (FFT). Abnormal sound of human screaming and glass breaking were classified using decision tree. From experiment, proposed abnormal sound analytical surveillance system test yield average of 88% accuracy detection. We can consider our work is simple and cost effective for field implementation.

Membrane separation based on ultrafiltration for the recovery of spent tungsten slurry from chemical mechanical polishing (CMP) process has been investigated. Five polymeric membranes with different molecular weight cut-off (MWCO) i.e. 10 kDa PES, 30 kDa PES, 100 kDa PES, 50 kDa PS and 50 kDa PVDF were successfully applied. Flux analysis was conducted to study the fouling phenomena and the fouling effects on membrane surface were elucidated by means of SEM and AFM analyses. Almost steady fluxes were reached after about 60 min of filtration process. Meanwhile, the membrane fouling was mainly due to the formation of cake layer on the membrane surface leading to blockage of membrane pores. On top of that, 50 kDa PS membrane showed the highest potential in filtrating and concentrating the CMP spent tungsten slurry with 92% retention of silica particles and 42% retention of tungsten. Furthermore, it also achieved the lowest mean size particle of 126 nm in the retentate which were significantly different from that of the original spent tungsten slurry.

Dispersing agents used during electrode position process are required to form stable suspension of solution at room temperature for controllable thickness of deposited materials. The solvent selected for dispersion of multi-walled carbon Nanotubes (MWCNTs) are mixture of acetone and ethanol, dimethyl formamide (DMF), N-methyl-2-pyrrolidone (NMP) and distilled water were investigated. Among these solvents, DMF shows better suspension stability and performed well during electrophoretic deposition (EPD) of MWCNTs on nickel substrate. Analysis by scanning electron microscopy (SEM) shows the maximum of 4.78 µm thick of MWCNTs deposited on nickel substrate when operated under150V applied voltage, 10 minutes deposition time for 0.50 mg/ml concentration.

This study investigates fluid–structure interaction (FSI) analysis of stacked chip in the encapsulation of molded underfill packaging using ANSYS Coupling Work bench with fluid and structural solvers. During encapsulation, FSI analysis is applied to a molded package with different layouts, namely cases 1–4 of stacked chip. An even ratio of inlet and outlet gate pressures is used to produce a regular melt front advancement. An experimental setup is fabricated to validate the simulation results in the FSI study. A digital camera is used to capture the melt front advancement and structural deformation. The interaction between structures (silicon chip) and epoxy molding compound (EMC) is displayed in the displacement profile. Maximum deformation is evaluated during the final stage of filling. The silicon die experiences von Mises stresses, which are monitored to observe the risk of die cracking. The results of this study showed that, the EMC flow front advancement was the fastest in case 4. The pressure distribution of each case was nearly identical, and the maximum von Mises stress was distributed unevenly at the middle of the stacked chip. The proposed analysis can serve as a reference and guide in designing and improving 3D integration packages in industry.

The fluid/structure interaction (FSI) investigations of stacked chip in encapsulation process of moulded underfill packaging using the two-way Coupling method with ANSYS Fluent and ANSYS Structural solvers are presented. The FSI study is executed with different aspect ratio of stacked chip on the mould filling during the encapsulation process. The simulation results in the FSI study is well validated with experimental setup. The epoxy moulding compound (EMC) and structure (chip) interaction is analyzed for better understanding the FSI phenomenon.Von Mises stresses experienced by the chip also be monitored for risk of chip cracking. The proposed analysis is anticipated to be a recommendation in the chip design and improvement of 3D integration packages.