A Metal-Insulator-Metal (MIM) capacitor with high capacitance, high breakdown voltage, and low leakage current is aspired so that the device can be applied in many electronic applications. The most significant factors that affect the MIM capacitor’s performance is the design and the dielectric materials used. In this study, MIM capacitors are simulated using different dielectric materials and different number of dielectric layers from two layers up to seven layers. The effect of the different dielectric constants (k) to the performance of the MIM capacitors is also studied, whereas this work investigates the effect of using low-k and high-k dielectric materials. The dielectric materials used in this study with high-k are Al2O3 and HfO2, while the low-k dielectric materials are SiO2 and Si3N4. The results demonstrate that the dielectric materials with high-k produce the highest capacitance. Results also show that metal-Al2O3 interfaces increase the performance of the MIM capacitors. By increasing the number of dielectric layers to seven stacks, the capacitance and breakdown voltage reach its highest value at 0.39 nF and 240 V, respectively.

This paper reports on the design, implementation, and characterization of a trench-filled capacitor in complementary Metal-Oxide-Semiconductor (CMOS) grade silicon. In order to achieve high capacitance value in MOS capacitor, trench technology is applied to improved capacitance. The simulation executed by using Synopsys's Sentaurus TCAD. A C-V measurement was done between two different structures of MOS capacitor which are using planar and trench technology. A MOS capacitor with planar technology achieved 4.5 fF meanwhile trench technology achieved a much higher capacitance which is 1.325 pF. A test of varied trench has also been carried out to verify the basic fundamentals of MOS capacitor. It shows that a deeper trench helps to increase higher capacitance.

This paper presents a modular architecture for dynamically reconfigurable middlebox with a customized reconfiguration handler. The data plane of this middlebox can be updated remotely at run-time by client to support post-deployment feature extension, customization and optimization. The proposed Reconfiguration Handler can achieve at least 3.19 Gbps of reconfiguration throughput, which reduces the platform service downtime during dynamic partial reconfiguration. In order to reduce the latency and transmission overhead of remote functional update, partial bitstream is compressed before transmission. The application of the proposed architecture is not limited to network processing as data analytics circuitries can be embedded into the data plane for big data applications.

Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, HTM performance is application-specific and determined by version and conflict management configurations. Most previous HTM implementations for embedded system in literature were built on fixed version management that result in significant performance loss when transaction behaviour changes. In this paper, we propose a HTM targeted for embedded applications which is able to adapt its version management based on application behaviour at runtime. It is prototyped and analysed on Altera Cyclone IV platform. Random requests at different contention levels and different transaction sizes are used to verify the performance of the proposed HTM. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up compared to eager version management at high contention level. Meanwhile, eager version management obtains up to 37.84% speed-up compared to lazy version management at low contention. The adaptive mechanism is able to switch configuration at runtime based on applications behaviour for maximum performance.

Incremental and Decremental Support Vector Machine (IDSVM) is a widely used incremental learning algorithm that is highly accurate but requires high computational complexity. For IDSVM to be deployed in embedded systems, moving window architecture is needed to limit the number of support vectors in the model. This increases the complexity of the system as data need to be unlearned while learning new data. This work proposes an interleaved IDSVM (IIDSVM) architecture that performs incremental and decremental learning simultaneously. This work targets embedded system platform with limited on-chip memory. The proposed solution is able to get an improvement of 60% - 70% in terms of speed while producing similar accuracy with IDSVM.

Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated SVM. SVM classification computational complexity makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, test data are stored on external memory and transferred in streams to the FPGA device. The hardware implementation for SVM classification needs to be fast enough to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in overall streaming architecture as maximum throughput could not be obtained. In this work, we propose a streaming architecture multi-class SVM classification for embedded system that is fully pipelined and able to process data continuously with out any need to throttle data stream input. The proposed design is targeted for embedded platform where test data is transferred in streams from an external memory. The architecture was implemented on Altera Cyclone IV platform. Performance analysis on our proposed architecture is done with regards to the number of features and support vectors. For validation, the results obtained is compared with LibSVM. The proposed architecture is able to produce output rate identical to test data input rate.

Routing algorithm has a significant impact on the overall performance of network-on-chip (NoC) based system due to the unbalanced nature of NoC traffic. In this paper, we propose an improved flow control for implementing fully adaptive routing algorithm on 2D mesh based NoC. Our proposed NoC router allows packet exchanges from escape virtual channels (EVCs) to adaptive VCs (AVCs). It also relaxes the atomic VC reallocation constraint for all EVCs as well as AVCs, which are located in router's local, east and west ports of the router. This approach guarantees that the abovementioned conditions still result in a deadlock-free routing. The proposed fully adaptive NoC outperforms the conventional fully adaptive router and partially adaptive router that uses odd-even routing by 80% and 25% higher average saturation injection ratio, respectively.

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a complete NoC-based MCSoC on a single FPGA device. FPGA prototyping allows rapid system verification and optimum design parameters estimation. However, existing NoC-based MCSoC prototypes are usually adopting simple NoC architectural functionality. These NoC prototypes cannot represent a realistic projection of the state-of-the-art application-specific integrated circuit (ASIC) NoCs as these prototypes have limited overall system performance. This paper presents ProNoC, an integrated tool for rapid prototyping and validation of NoC-based MCSoC projects targeting FPGA devices. ProNoC adopts most advanced NoC features such as the support of virtual channel (VC), virtual network, low latency routing and different routing algorithms. Results show that NoC interconnect in ProNoC outperforms CONNECT, the most recent VC based prototype NoC with lower logic cell utilization, higher maximum operating frequency, higher average saturation throughput, and lower average communication latency. Moreover, ProNoC is equipped with graphical user interface to facilitate the development of MCSoC prototypes on FPGA platforms.