This research presents the development of simulation modeling for WIP management in semiconductor fabrication. Manufacturing simulation modeling is needed for productivity optimization analysis due to the complex process flows involved more than 35 percent re-entrance processing steps more than 15 times at same equipment. Furthermore, semiconductor fabrication required to produce high product mixed with total processing steps varies from 300 to 800 steps and cycle time between 30 to 70 days. Besides the complexity, expansive wafer cost that potentially impact the company profits margin once miss due date is another motivation to explore options to experiment any analysis using simulation modeling. In this paper, the simulation model is developed using existing commercial software platform AutoSched AP, with customized integration with Manufacturing Execution Systems (MES) and Advanced Productivity Family (APF) for data collections used to configure the model parameters and data source. Model parameters such as processing steps cycle time, equipment performance, handling time, efficiency of operator are collected through this customization. Once the parameters are validated, few customizations are made to ensure the prior model is executed. The accuracy for the simulation model is validated with the actual output per day for all equipments. The comparison analysis from result of the simulation model compared to actual for achieved 95 percent accuracy for 30 days. This model later was used to perform various what if analysis to understand impacts on cycle time and overall output. By using this simulation model, complex manufacturing environment like semiconductor fabrication (fab) now have alternative source of validation for any new requirements impact analysis.

This research is to investigate simulation modeling method for semiconductor fabrication factories (FAB) that known for complex manufacturing operation from various the literatures. This paper covers literatures from various publications since past 10 years. The significant simulation model used in common and semiconductor fabrication will be selected for evaluation in semiconductor fabrication manufacturing operation scenario with high mixed. Depends to the products mixed configuration, cycle time to complete semiconductor fabrication will take 60 to 90 days. The longer period needed due to wafer process required 300 to 1000 steps, process re-entrance to similar equipment more than 30% of the total steps further increase the complexity with many configuration due to setup changes. The simulation also needs to configure for process queue time, process dedication, several of difference for equipment configuration, capability and capacity. Primary simulation techniques reviewed in this analysis are discrete event, petri-net, gaming, virtual, intelligent, monte carlo and hybrid to understand individual strength and common usage in the market. This research summarized the highest usage, most uses and compatibility in similar operation for semiconductor fabrication. In summary, the research concluded DES is the most suitable technique for simulating FAB operation because of its nature of queuing and leaving concept that fits and resulted to 95% accuracy for WIP forecasting.

Cycle time for a product is one of the key performance indicators in semiconductor manufacturing. Reduction of cycle time will shorten product time to market, increase throughput, reduce operational cost and develop customer trust. Semiconductor manufacturing that process 40,000 to 50,000 work-in-progresses (WIP), usually takes 50 to 70 days, 300 to 400 equipments and 300 to 900 steps to complete. Thus, any task related to manual data collection to make indices reports or analysis usually needs high resources requirements to spend for manual work and risk for mistake. In the modern facility of semiconductor fabrication, a system like Manufacturing Execution Systems (MES) was implemented to ease the process and operation traceability. The information is well kept in the appropriate databases. Many applications then are integrated with MES database to perform indices reports. In this paper, the improve method for data collection related to cycle time improvement is introduced. In this approach, the automated systems was developed using existing Advance Productivity Family (APF) programming platform to collecting the data. The system is integrated between MES and APF to have the real time data collection and analysis. In the systems, manual data collection is replaced with respective automated data transfer from real situation in the manufacturing environment. This program then able to shows real root caused with proper relational charting to display real problem for engineering to prioritize and resolve respectively. As a result, 39% reduction of cycle time gained by implementing this technique. The system has successfully implemented and supports the cycle time reduction.

A typical semiconductor fabrication process contains 300 to 1000 steps and its variation depends on the product complexity. Most of the processes are re-entrance to same equipments especially at photolithography, etching, implanter, film deposition, chemical mechanical polishing (CMP) and cleaning. For example, photolithography steps for island, poly, and contact module will be processed at same equipment. Another complication is that the equipment types are different from one to another resulting in different approach for cycle time calculation, difference in availability and efficiency. The objective of this paper is to establish capacity indices to guide for monthly output in semiconductor fabrication facilities. The approach in this paper is using the waterfall chart for individual process and equipment types. Data extraction is being done through reporting systems of Advance Productivity Family (APF), an industrial standard software for data collection that is integrated with individual equipment and product processing historical data. The data was then analyzed using JMP to check for sanity. Results were used to develop capacity indices, which are wafer per hour (wph), manufacturing efficiency, and equipment availability. All these information will be later used to develop the final capacity figure. The final capacity number will then be used to guide the planning team to schedule product combination that will achieve monthly and quarterly wafer shipment goal to customers. This approach reached accuracy of 99% compared to actual throughput. In conclusion, this approach helps the company to provide planning guidelines in meeting the financial goals.

Modification of current density in back-to-back Schottky contacts without further heat treatment processes is possible by embedding nanoparticles (NPs) into metal contacts with different work functions. In this work n-type Silicon (n-Si) back-to-back aluminum (Al) Schottky contacts embedded with gold (Au) NPs were fabricated using spin-coating technique. The effect of embedded NPs on the electrical properties were subsequently studied by current-voltage parameter analyzer. Effect of the density of Au NPs on Schottky barrier lowering and current density enhancement of the contacts were also studied and the energy band bending mechanism of Al/Si contacts with and without the NPs effect was proposed and discussed. The electrical results showed that by increasing the density of Au NPs spin-coated on Si, the current density in both bias directions has increased by more than two orders of magnitude. The increase in current density was attributed to the effect of NPs in electric field enhancement which subsequently resulted in Schottky barrier thinning and facilitation of field emission conduction and hence current density elevation.

Embedding metal nanoparticles (NPs) into metal contacts at metal–Si (MS) interface is an alternative method for modification of Schottky barrier height (SBH) and compared with traditional methods that might result in an undesired alteration of the MS interface, offers a tremendous simplification and adaptation in processing steps. There is a direct link between the type, size and density of NPs and their interaction with contact/semiconductor and the improved electrical characteristics. A comprehensive analysis of the NPs effect at MS interface is required to make appropriate and efficient selection of contact/NPs combination as well as deposition of NPs and fabrication of nanostructured contact. In this work, multiple successive deposition of colloidal Au NPs by spin-coating is used as an alternative and simple method to deposit Au NPs on n- and p-Si substrates. Electrical parameters of Au NPs/Al nanostructured contacts including SBH and ideality factor are in turn extracted from current–voltage characteristics. Two models of inhomogeneity in SBH and enhanced tunneling at triple interface are then invoked for further analysis of the NPs effect on electrical properties of contacts. The best model proposed to describe this phenomenology is the enhanced tunneling at triple interface.

Nanostructured contacts, comprised of nanoparticles (NPs) embedded at the interface of contact/semiconductor, offer a viable solution in modification of Schottky barrier height (SBH) in Schottky contacts. The successful performance of devices with such nanostructured contacts requires a feasible selection of NPs/contact material based on theoretical calculations and a cost effective and reproducible route for NPs deposition. Acidification of commercially available colloidal Au NPs solution by HF has been selected here as a simple bench-top technique for deposition of Au NPs on n- and p-type 4H-SiC substrates. Theoretical calculations based on the model of inhomogeneity in SBH (ISBH) were used to make a more appropriate selection of NPs type (Au) and size (5 and 10 nm, diameter) with respect to contact metal (Al). Al/Au NPs/SiC Schottky barrier diodes were then fabricated, and their electrical characteristics exhibited current density enhancement due to the SBH lowering. The source of SBH lowering was determined to be the local electric field enhancement due to NPs effect, which was further investigated using the models of ISBH and tunneling enhancement at triple interface.

Colloidal gold (Au) nanoparticles (NPs) deposition on silicon (Si) substrate is highly affected by the deposition technique and surface properties of the substrate. Spin-coating technique has been proven to be an efficient approach in terms of cost, time and maintaining the quality of the deposition. However, to prevent the agglomeration of NPs and obtain desirable density and distribution of NPs on the substrate, precise control of the spin-coating parameters is required. In this study colloidal Au NPs were spin-coated onto a modified, yet linker-free Si surface. By controlling the spinning speed, acceleration, dwelling time, and the volume of NPs colloidal solution, the density and distribution of the NPs on Si were optimized. Scanning electron microscope was used to investigate the NPs density in each step of the process. Results showed that the distribution of NPs on Si substrate is highly dependent on the spinning speed, duration, and acceleration rate as well as surface properties of Si substrate.