This brief describes a novel Wideband Pre-Distortion (WPD) mechanism as a linearization technique for bandwidth-limited CMOS power amplifiers (PAs). The WPD comprises a common-source amplifier and a hybrid feedback mechanism blended with both active and passive networks to secure a flat gain response from 800 MHz till 3.3 GHz, while maintaining >30% power added efficiency (PAE) at a maximum linear output power of 20 dBm throughout the band of operation. The WPD generates unique gain and phase cancellation mechanisms on-chip therefore alleviating the 3rd-order intermodulation product (IMD3) for an operating bandwidth of 2.5 GHz. Measurement results on 180 nm CMOS, with a supply voltage of 3.3 V indicate that the WPD-PA produces a saturated output power of 24 dBm, in addition to a power gain of 15.5 dB and a peak efficiency of 35.5% at 2.45 GHz. The WPD-PA delivers a maximum linear output power of 20-dBm with an adjacent channel leakage ratio (ACLR) of -30 dBc and error vector magnitude (EVM) of 3.42%, 2.34% and 2.76% at 0.8, 2.45 and 3.3 GHz when measured with the 20-MHz LTE signal. The corresponding maximum linear PAE ranged between 31 to 34%. The chip area is 1.28 mm2.

Wireless communication standard continues to evolve in order to fulfill the demand for high data rate operation. This leads to the exertion on the design of radio frequency power amplifier (RFPA) which consumes high DC power in order to support linear transmission of high data rate signal. Hence, operating the PA with low DC power consumption without trading-off the linearity is vital in order to achieve the goal of achieving fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the evolution of CMOS PA toward achieving a fully integrated transceiver solution is discussed through the review of multifarious CMOS PA design. This is categorized into the review of efficiency enhancement designs followed by linearity enhancement designs of the CMOS PA.

Post-fabrication inductance variation is a big issue faced by chip designers of sensitive circuits, and on-chip tunable inductors seem to provide the solution to this problem. In addition, tunable inductors also benefit circuits that require the multi-frequency operation. This paper is on the design of a tunable inductor which utilizes the patterned ground shield (PGS) to enable fine-tuning capability. This work is unique as this is the first time that the PGS is used for this purpose, previous researches were more on the Q-factor merit provided by the inductors with PGS. In this work, inductor's and PGS parameters influencing the inductance tuning range and Q-factor performances were first determined. Subsequently, inductors with PGS made from different metals and track spacing were designed, with electronic circuitries implemented to control the grounding of each PGS metal finger. The hypothesis that the floating and grounding of each PGS metal finger can change the magnetic flux of the inductor which contributes to the inductance variation was verified using Sonnet EM. Measured results show that a 5.2% inductance tuning range and Q-factor of 5.9 were achieved at the Bluetooth frequency of 2.5 GHz for an inductor with 2.0 µm track spacing and a polysilicon PGS with finger spacing of 2.0 µm. The tunable inductor was further integrated into a power amplifier (PA) and simulation results show that it enables the PA to achieve the design specification at the frequency range of 3.3–3.8 GHz, dedicated for the sub-6 GHz 5G application.

Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49 % of the overall efficiency from the transmitter. Hence, operating the PA with minimum power consumption without trading-off the linearity is vital in order to achieve the goal of fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the efficiency in CMOS PA is discussed through the review of multifarious efficiency enhancement techniques in CMOS PA design. This is categorized into the review of efficiency in fundamental classes of PA in which Class E achieves the highest efficiency of 67 %, followed by complex architectures utilized to enhance the efficiency level of the PA in which the outphasing architecture achieved the highest efficiency of 60.7 %.

This article describes a novel Low Power Current Source Tunable Inductor (LPCSTI) for CMOS Radio Frequency Integrated Circuits (RFIC). The LPCSTI comprises a deep triode common source transistor, a stabilizer resistor and a coupling capacitor which is capable to increase the physical inductance value up to 80% from its default value thus achieving higher inductance per area. Integration of the tuner to a physical inductor of 1.2 nH increases the inductance value up to 2.2 nH at 2.5 GHz, contributing to an area reduction of 52%. The LPCSTI is implemented in a single stage CMOS 180 nm power amplifier (PA) and tested. The tunability property of the LPCSTI allows the performance of the LPCSTI-PA to be adjusted and makes it resilient to process variations, thus enhances production yield. The LPCSTI-PA achieved a maximum output power of 15 dBm as well as peak efficiency of 45%. Measurement on 10 sample dice show that the efficiency of the LPCSTI-PA can be maintained to be more than 20% at maximum linear output power.

A low power consumption linear power amplifier (PA) for Internet of Things (IoT) application is presented. An analog pre-distorter (APD) is integrated to the PA, which consists of an active inductor, driver amplifier, and an RC phase linearizer. When measured with continuous wave signal, the PA produces more than 12 dB power gain from 2.4 to 2.5 GHz. At the centre frequency of 2.45 GHz, the PA’s gain is 12.5 dB with peak power added efficiency (PAE) of 25.6% and maximum output power of 13.7 dBm. The OIP3 achieved is 29.2 dBm with supply voltage headroom of 1.8 V. The proposed APD befit to be a solution to reduce the trade-off between maximum linear output power and PAE.

Intelligent Transportation System (ITS) consisting of Vehicle Ad-hoc Networks (VANET) offers a major role in ensuring a safer environment in cities for drivers and pedestrians. VANET has been classified into two main parts which are Vehicle to Infrastructure (V2I) along with Vehicle to Vehicle (V2V) Communication System. This technology is still in development and has not been fully implemented worldwide. Currently, Dedicated Short Range Communication (DSRC) is a commonly used module for this system. This paper focuses on both V2V and V2I latest findings done by previous researcher and describes the operation of DSRC along with its architecture including SAE J2735, Basic Safety Message (BSM) and different type of Wireless Access in Vehicular Environment (WAVE) which is being labeled as IEEE 802.11p. Interestingly, (i) DSRC technology has been significantly evolved from electronic toll collector application to other V2V and V2I applications such as Emergency Electronics Brake Lights (EEBL), Forward Collision Warning (FCW), Intersection Moving Assist (IMA), Left Turn Assist (LTA) and Do Not Pass Warning (DNPW) (ii) DSRC operates at different standards and frequencies subject to the country regulations (e.g. ITS-G5A for Europe (5.875–5.905 GHz), US (5.850–5.925 GHz), Japan (755.5–764.5 MHz) and most other countries (5.855–5.925 GHz)) where the frequencies affected most on the radius of coverage.

A five-Port Reflectometer (FPR) with the integration of ultra-wideband (UWB) Epsilon Negative (ENG) Double Split Ring Resonator (DSRR) metamaterial array is introduced in this paper for microwave imaging (MWI) application. The designed DSRR consists of two concentric rings with a split in each which are spatially rotated by 180°, formed an inverted structure to exhibit a wide negative epsilon bandwidth of 187 % (from 0.5 GHz to 15 GHz). The FPR is designed using a ring junction topology and semi-circularly curved inter-port transmission lines (TLs) which are placed between five equally spaced ports. Localizing the DSRR metamaterial in a periodic array of 5 × 4 at the ground plane of FPR lead to 79.79 % fractional bandwidth and reflection coefficient within the operating frequencies of 0.991 GHz–2.2576 GHz. Equivalent circuit model has been alluded with an intricate description of different array configurations of the metamaterial unit cell. Comparison of EM simulation and circuit simulation has been performed to validate the equivalent circuit model. It is found that the existence of stray capacitance,